From 05bf7f25041cbd801ef82d93b0db324929f7a30a Mon Sep 17 00:00:00 2001
From: Alexander Binzberger <alexander@binzberger.de>
Date: Fri, 3 Aug 2018 23:52:19 +0200
Subject: [PATCH] adding cTDP configuration option

---
 etc/lenovo_fix.conf |  4 ++++
 lenovo_fix.py       | 10 ++++++++++
 2 files changed, 14 insertions(+)

diff --git a/etc/lenovo_fix.conf b/etc/lenovo_fix.conf
index 8077db8..94e5d80 100644
--- a/etc/lenovo_fix.conf
+++ b/etc/lenovo_fix.conf
@@ -15,6 +15,8 @@ PL2_Tdp_W: 44
 PL2_Duration_S: 0.002
 # Max allowed temperature before throttling
 Trip_Temp_C: 85
+# Set cTDP to normal=0, down=1 or up=2 (EXPERIMENTAL)
+cTDP: 0
 
 ## Settings to apply while connected to AC power
 [AC]
@@ -32,6 +34,8 @@ PL2_Duration_S: 0.002
 Trip_Temp_C: 95
 # Set HWP energy performance hints to 'performance' on high load (EXPERIMENTAL)
 HWP_Mode: False
+# Set cTDP to normal=0, down=1 or up=2 (EXPERIMENTAL)
+cTDP: 0
 
 [UNDERVOLT]
 # CPU core voltage offset (mV)
diff --git a/lenovo_fix.py b/lenovo_fix.py
index df0cc1a..4df04d5 100755
--- a/lenovo_fix.py
+++ b/lenovo_fix.py
@@ -33,6 +33,7 @@ VOLTAGE_PLANES = {
 }
 
 TRIP_TEMP_RANGE = (40, 97)
+C_TDP_RANGE = (0, 2)
 
 power = {'source': None, 'method': 'polling'}
 
@@ -137,6 +138,11 @@ def calc_reg_values(config):
         regs[power_source]['MSR_PKG_POWER_LIMIT'] = PL1 | (1 << 15) | (TW1 << 17) | (PL2 << 32) | (1 << 47) | (
             TW2 << 49)
 
+        # cTDP
+        c_tdp_target_value = int(config.getfloat(power_source, 'cTDP'))
+        valid_c_tdp_target_value = valid_trip_temp = min(C_TDP_RANGE[1], max(C_TDP_RANGE[0], c_tdp_target_value))
+        regs[power_source]['MSR_CONFIG_TDP_CONTROL'] = valid_c_tdp_target_value
+
     return regs
 
 
@@ -164,6 +170,10 @@ def power_thread(config, regs, exit_event):
         # set temperature trip point
         writemsr(0x1a2, regs[power['source']]['MSR_TEMPERATURE_TARGET'])
 
+        # set cTDP
+        # TODO read MSR 0xCE to check if the operation is possible
+        writemsr(0x64b, regs[power['source']]['MSR_CONFIG_TDP_CONTROL'])
+
         # set PL1/2 on MSR
         writemsr(0x610, regs[power['source']]['MSR_PKG_POWER_LIMIT'])
         # set MCHBAR register to the same PL1/2 values