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adding cTDP configuration option

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This commit is contained in:
Alexander Binzberger
2018-08-03 23:52:19 +02:00
parent 3a65e10c69
commit 05bf7f2504
2 changed files with 14 additions and 0 deletions
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4
etc/lenovo_fix.conf
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@@ -15,6 +15,8 @@ PL2_Tdp_W: 44
PL2_Duration_S: 0.002 PL2_Duration_S: 0.002
# Max allowed temperature before throttling # Max allowed temperature before throttling
Trip_Temp_C: 85 Trip_Temp_C: 85
# Set cTDP to normal=0, down=1 or up=2 (EXPERIMENTAL)
cTDP: 0
## Settings to apply while connected to AC power ## Settings to apply while connected to AC power
[AC] [AC]
@@ -32,6 +34,8 @@ PL2_Duration_S: 0.002
Trip_Temp_C: 95 Trip_Temp_C: 95
# Set HWP energy performance hints to 'performance' on high load (EXPERIMENTAL) # Set HWP energy performance hints to 'performance' on high load (EXPERIMENTAL)
HWP_Mode: False HWP_Mode: False
# Set cTDP to normal=0, down=1 or up=2 (EXPERIMENTAL)
cTDP: 0
[UNDERVOLT] [UNDERVOLT]
# CPU core voltage offset (mV) # CPU core voltage offset (mV)

10
lenovo_fix.py
View File

@@ -33,6 +33,7 @@ VOLTAGE_PLANES = {
} }
TRIP_TEMP_RANGE = (40, 97) TRIP_TEMP_RANGE = (40, 97)
C_TDP_RANGE = (0, 2)
power = {'source': None, 'method': 'polling'} power = {'source': None, 'method': 'polling'}
@@ -137,6 +138,11 @@ def calc_reg_values(config):
regs[power_source]['MSR_PKG_POWER_LIMIT'] = PL1 | (1 << 15) | (TW1 << 17) | (PL2 << 32) | (1 << 47) | ( regs[power_source]['MSR_PKG_POWER_LIMIT'] = PL1 | (1 << 15) | (TW1 << 17) | (PL2 << 32) | (1 << 47) | (
TW2 << 49) TW2 << 49)
# cTDP
c_tdp_target_value = int(config.getfloat(power_source, 'cTDP'))
valid_c_tdp_target_value = valid_trip_temp = min(C_TDP_RANGE[1], max(C_TDP_RANGE[0], c_tdp_target_value))
regs[power_source]['MSR_CONFIG_TDP_CONTROL'] = valid_c_tdp_target_value
return regs return regs
@@ -164,6 +170,10 @@ def power_thread(config, regs, exit_event):
# set temperature trip point # set temperature trip point
writemsr(0x1a2, regs[power['source']]['MSR_TEMPERATURE_TARGET']) writemsr(0x1a2, regs[power['source']]['MSR_TEMPERATURE_TARGET'])
# set cTDP
# TODO read MSR 0xCE to check if the operation is possible
writemsr(0x64b, regs[power['source']]['MSR_CONFIG_TDP_CONTROL'])
# set PL1/2 on MSR # set PL1/2 on MSR
writemsr(0x610, regs[power['source']]['MSR_PKG_POWER_LIMIT']) writemsr(0x610, regs[power['source']]['MSR_PKG_POWER_LIMIT'])
# set MCHBAR register to the same PL1/2 values # set MCHBAR register to the same PL1/2 values